XConn Technologies and ScaleFlux announced they have successfully optimized performance and achieved interoperability between XConn’s CXL® 3.1 switch and ScaleFlux’s MC500 CXL 3.1 Type 3 memory controller. The two companies will showcase this joint achievement at the Future of Memory and Storage (FMS25) event at the Santa Clara Convention Center.
This collaboration marks a significant milestone in enabling memory disaggregation and pooling capabilities for AI and cloud infrastructure at scale. The combined solution leverages the reliability and low latency of the XConn hybrid PCIe® / CXL® switch and the advanced ECC and RAS features of the ScaleFlux MC500 to deliver industry-leading composable memory performance.
“This is a major step forward for the Compute Express Link® (CXL) ecosystem,” said Gerry Fan, CEO of XConn Technologies. “By optimizing our CXL 3.1 switch to work seamlessly with ScaleFlux’s MC500 memory controller, we’re giving customers a production-ready path to unlock the full potential of CXL-based memory pooling and disaggregation in AI and cloud environments.”
The ScaleFlux MC500 CXL 3.1 Type 3 controller, developed in close collaboration with hyperscalers, memory providers, and CPU vendors, introduces a groundbreaking list decoding ECC architecture to deliver unmatched reliability, availability, and serviceability (RAS) in DRAM-based memory systems. Combined with production-grade, turnkey firmware, the MC500 accelerates deployment for data centers adopting CXL memory infrastructure.
“Our partnership with XConn underscores our commitment to building a robust and interoperable CXL ecosystem,” said Hao Zhong, CEO and Co-founder of ScaleFlux. “The combination of our MC500 controller’s advanced ECC technology and XConn’s hybrid CXL 3.1 switch offers data centers and AI infrastructure providers a highly reliable, low-latency solution to efficiently scale memory capacity and bandwidth for their AI and enterprise applications.”
The joint demonstration at FMS25 will showcase a fully functional system featuring AMD processors, the XConn CXL 3.1 switch, and the ScaleFlux MC500 memory controller working together to power a high-performance, disaggregated memory platform.
“CXL is critical to accelerating the development of next-generation memory and compute technologies powering critical AI and HPC workloads,” said Raghu Nambiar, corporate vice president, Data Center Ecosystems and Solutions, AMD. “Our collaboration with XConn and ScaleFlux strengthens ecosystem interoperability efforts that enable memory disaggregation and infrastructure flexibility for the modern AI data center.”
With this announcement, XConn continues its mission to accelerate the adoption of CXL 3.1 infrastructure through standards-based innovation, ecosystem collaboration, and customer-ready solutions that scale with the performance demands of next-generation AI and cloud applications.
XConn will also be presenting during FMS25, furthering industry advocacy for the advancement of the CXL standard. Jianping Jiang, Senior Vice President, Business Development will be among the panelists to deliver the session “How CXL Transforms Server Memory Infrastructure” at 9:45 a.m. on Wednesday, August 6.
To learn more about XConn Technologies and ScaleFlux MC500 partnership, visit the website here.
XConn additionally announced that it will deliver an end-to-end PCIe Gen 6 demonstration during FMS25; learn more here.
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