Marvell announced it is extending its data infrastructure silicon leadership with a new advanced silicon platform based on TSMC’s 3nm process technology, offering the best power, performance, and area in the industry. Marvell will have IP cores on upcoming TSMC 3nm silicon releases, enabling its customers to take advantage of the world’s most advanced semiconductor technologies in conjunction with other proven silicon components to build unique, complex, system-optimized solutions that meet the most demanding cost, performance and power requirements in cloud data center, 5G carrier, automotive and enterprise markets.
Marvell is first to introduce a comprehensive standards-based silicon platform for multi-chip solutions that leverages the latest process technology, advanced die-to-die interface IP, and TSMC’s advanced 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging technology.
In addition to the extensive IP portfolio offered by Marvell, the new TSMC 3nm multi-chip platform includes two complementary advanced die-to-die interfaces. The first is a flexible extra short reach (XSR) interface for connecting multiple die on a package substrate for applications, like co-packaged optics (CPO) for cloud data centers. To address the growing needs for cloud-optimized silicon solutions from leading data center operators, Marvell is also developing an ultra-low power and low-latency parallel die-to-die interface with the highest bandwidth density in the industry. Compatible with emerging Open Compute Project (OCP) standards, the new parallel interface enables high-performance chiplet solutions by connecting multiple silicon devices on an interposer. Both interfaces are also available in 5nm to enable multi-node solutions.
The new platform also incorporates TSMC’s advanced CoWoS packaging technology, empowering continued data infrastructure performance scaling. Marvell’s collaboration with TSMC on CoWoS allows customers to build high-performance solutions for the most demanding cloud data center applications.
“Marvell is proud to be the lead vendor to offer a 3nm platform for cloud-optimized solutions,” said Sandeep Bharathi, Executive Vice President, Central Engineering, System-on-Chip Group at Marvell. “Our new advanced node platform places Marvell on the leading edge of technology readiness with early Si validation of critical IPs to enable fast time-to-market.”
Availability
Marvell is currently engaged and collaborating with all the leading data infrastructure innovators. To learn more, please visit: https://www.marvell.com/products/custom-asic.html.
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