XConn Apollo Interconnect Solution Showcased at TSMC 2024

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XConn Technologies revealed plans to display initial production samples of its “Apollo” CXL 2.0 / PCIe Gen 5 hybrid switch at the TSMC 2024 North America Technology Symposium on April 24 in Santa Clara, California.

As the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 interconnect solution, the XConn Apollo switch is purpose-built to simplify the system designer process with versatile expansion and heterogeneous integration for a mix of accelerators and fault tolerance with the redundancy mission-critical applications require for true processing availability. This makes the Apollo interconnect solution ideal for use in high demand artificial intelligence (AI) application environments.

XConn has been working closely with TSMC, the world’s leading dedicated foundry, to make its XConn Apollo on TSMC’s industry leading process technologies from N16 to N5. “TSMC’s robust manufacturing and efficient project management for timely delivery enable us to sharply focus on our product design and technology development,” said Gerry Fan, President and CEO of XConn Technologies. “TSMC is our trusted foundry partner that helps us deliver our industry leading connectivity product to meet the ever-growing demands in the AI and computing markets.”

“TSMC is committed to partnering with innovators like XConn to advance their next generation interconnect technology,” said Lucas Tsai, Senior Director of Market Development and Emerging Business Management, TSMC North America. “Our industry-leading technologies and manufacturing excellence enable XConn to accelerate their chip innovation and to facilitate the rapid growth in data transmission that comes with the AI boom.”

The Apollo switch is innovative in its design, offering system developers the opportunity to future-proof devices to capitalize on the breakthrough performance of new CXL interconnect technology with the industry’s first CXL 2.0 switch, while also supporting PCIe 5.0 standards. Both PCIe and CXL can now be supported in a single design. With 2,048 GB/s of total bandwidth and 256 lanes, the chip offers unprecedented flexibility for system designers that want to capitalize on JBOG (Just-a-Bunch-Of-GPUs) and JBOA (Just-a-Bunch-Of-Accelerators) processing configurations.

Available now in production samples, XConn Apollo delivers full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode. For customer samples and/or Apollo reference boards, or to learn more about XConn’s interconnect solution, visit the XConn website here.

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